Inventor · Hsinchu, TW

Chii-Ping Chen

40Patents
5h-index
46Co-inventors
69Inventor score

Filing activity: Jan 30, 2003 → Aug 10, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US8304906B2 Partial air gap formation for providing interconnect isolation in integrated circuits Electricity 18 Active
US6756309B1 Feed forward process control method for adjusting metal line Rs Electricity 12 Expired
US6949007B1 System and method for multi-stage process control in film removal Performing Operations; Transporting 5 Expired
US8436473B2 Integrated circuits including air gaps around interconnect structures, and fabrication methods thereof Electricity 5 Active
US10985011B2 Structure and formation method of semiconductor device with resistive elements Electricity 5 Active
US10304772B2 Semiconductor device structure with resistive element Electricity 5 Active
US8617986B2 Integrated circuits and methods for forming the integrated circuits Electricity 4 Active
US11404369B2 Semiconductor device structure with resistive element Electricity 4 Active
US11217482B2 Method for forming semiconductor device with resistive element Electricity 3 Active
US9496217B2 Method and apparatus of forming a via Electricity 3 Active
US11551968B2 Inter-wire cavity for low capacitance Electricity 2 Active
US11694926B2 Barrier free interface between beol interconnects Electricity 2 Active
US10515852B2 Structure and formation method of semiconductor device with resistive element Electricity 2 Active
US9257279B2 Mask treatment for double patterning design Electricity 1 Active
US11798848B2 Semiconductor device structure with resistive element Electricity 1 Active
US10164002B2 Semiconductor device and layout method Electricity 1 Active
US11342222B2 Self-aligned scheme for semiconductor device and method of forming the same Electricity 1 Active
US11362035B2 Diffusion barrier layer for conductive via to decrease contact resistance Electricity 0 Active
US12165947B2 Semiconductor devices and method for forming the same Electricity 0 Active
US11830770B2 Self-aligned scheme for semiconductor device and method of forming the same Electricity 0 Active
US12040178B2 Method for manufacturing semiconductor structure with resistive elements Electricity 0 Active
US12368103B2 Diffusion barrier layer for conductive via to decrease contact resistance Electricity 0 Active
US8499261B2 Method and apparatus of patterning semiconductor device Physics 0 Active
US8716862B2 Integrated circuit including a gate and a metallic connecting line Electricity 0 Active
US9553043B2 Interconnect structure having smaller transition layer via Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.