Sidewall wetting barrier for conductive pillars
US11694982B2 · kind B2 · utility
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30Claims
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Assignee
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Key dates
| Filing date | Feb 25, 2021 |
| Grant date | Jul 4, 2023 |
| Priority date | — |
| Expiry date | Feb 25, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3841
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are examples of integrated circuit (IC) structures and techniques to fabricate IC structures. Each IC package may include a die (e.g., a flip-chip (FC) die) and one or more die interconnects to electrically couple the die to a substrate. The die interconnect may include a pillar, a wetting barrier on the pillar, and a solder cap on the wetting barrier. The wetting barrier may be wider than the pillar. The die interconnect may also include a low wetting layer formed on the wetting barrier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.