Gate contact structure for semiconductor device

US11695069B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Markus Zundel · Egmating, DE
• Stefan Mieslinger · Kottgeisering, DE
• Thomas Ostermann · Velden am Wörther See, AT
• Andrew Christopher Graeme Wood · St. Jakob im Rosental, AT

Key dates

• Filing date: May 10, 2021
• Grant date: Jul 4, 2023
• Expiry date: Sep 30, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/513

Abstract

According to an embodiment of a semiconductor device, the semiconductor device includes: a first active cell area comprising a first plurality of parallel gate trenches; a second active cell area comprising a second plurality of parallel gate trenches; and a metallization layer above the first and the second active cell areas. The metallization layer includes: a first part contacting a semiconductor mesa region between the plurality of parallel gate trenches in the first and the second active cell areas; and a second part surrounding the first part. The second part of the metallization layer contacts the first plurality of gate trenches along a first direction and the second plurality of gate trenches along a second direction different from the first direction.