Distortion reduction circuit
US11695424B2 · kind B2 · utility
0Cited by
8References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2021 |
| Grant date | Jul 4, 2023 |
| Priority date | — |
| Expiry date | Nov 23, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/146
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a sampling circuit, a sense circuit, and a tuning circuit. The sampling circuit samples an input signal according to a sampling clock signal to produce a sampled signal. The sense circuit determines a scaling factor based on a distortion in the sampled signal caused by the sampling clock signal. The tuning circuit generates an offset signal based on the sampling clock signal and the scaling factor. The offset signal reduces the distortion in the sampled signal caused by the sampling clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.