Semiconductor integrated circuit and method of testing the same
US11698410B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2021 |
| Grant date | Jul 11, 2023 |
| Priority date | — |
| Expiry date | Sep 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.