Method for fabricating a heterostructure comprising active or passive elementary structure made of III-V material on the surface of a silicon-based substrate
US11698488B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2018 |
| Grant date | Jul 11, 2023 |
| Priority date | — |
| Expiry date | Feb 4, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L25/0753
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A process for fabricating a heterostructure includes at least one elementary structure made of III-V material on the surface of a silicon-based substrate successively comprising: producing a first pattern having at least a first opening in a dielectric material on the surface of a first silicon-based substrate; a first operation for epitaxy of at least one III-V material so as to define at least one elementary base layer made of III-V material in the at least first opening; producing a second pattern in a dielectric material so as to define at least a second opening having an overlap with the elementary base layer; a second operation for epitaxy of at least one III-V material on the surface of at least the elementary base layer made of III-V material(s) so as to produce the at least elementary structure made of III-V material(s) having an outer face; an operation for transferring and assembling the at least photonic active elementary structure via its outer face, on an interface that may comprise passive elements and/or active elements, the interface being produced on the surface of a second silicon-based substrate; removing the first silicon-based substrate and the at least elemen…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.