Inventor · Moirans, FR

Fabrice Nemouchi

32Patents
3h-index
32Co-inventors
59Inventor score

Filing activity: Sep 29, 2008 → Oct 14, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US8470689B2 Method for forming a multilayer structure Performing Operations; Transporting 197 Active
US7842612B2 Selective formation of a compound comprising a semi-conducting material and a metallic material in a substrate through a germanium oxide layer Electricity 6 Active
US8664104B2 Method of producing a device with transistors strained by means of an external layer Electricity 3 Active
US9269570B2 Contact on a heterogeneous semiconductor substrate Electricity 3 Active
US8617908B2 Method for producing a substrate including a step of thinning with stop when a porous zone is detected Electricity 3 Active
US8586463B2 Method for preparing a layer comprising nickel monosilicide NiSi on a substrate comprising silicon Electricity 2 Active
US7972911B1 Method for forming metallic materials comprising semi-conductors Electricity 2 Active
US10340361B2 Forming of a MOS transistor based on a two-dimensional semiconductor material Electricity 1 Active
US9093552B2 Manufacturing method for a device with transistors strained by silicidation of source and drain zones Electricity 1 Active
US11217446B2 Method for fabricating an integrated circuit including a NMOS transistor and a PMOS transistor Electricity 1 Active
US9548210B2 Fabrication method of a transistor with improved field effect Electricity 1 Active
US10930562B2 Internal via with improved contact for upper semi-conductor layer of a 3D circuit Electricity 0 Active
US11698488B2 Method for fabricating a heterostructure comprising active or passive elementary structure made of III-V material on the surface of a silicon-based substrate Electricity 0 Active
US11941485B2 Method of making a quantum device Physics 0 Active
US10388653B2 Formation of Ohmic contacts for a device provided with a region made of III-V material and a region made of another semiconductor material Electricity 0 Active
US12402542B2 Josephson transistor Electricity 0 Active
US11387147B2 Method for producing a component by filling a cavity within an electrical isolation area with carbon-based material Electricity 0 Active
US12417919B2 Method for producing a superconducting vanadium silicide on a silicon layer Electricity 0 Active
US11631739B2 Transistor having blocks of source and drain silicides near the channel Electricity 0 Active
US9831319B2 Transistor with MIS connections and fabricating process Electricity 0 Active
US11515148B2 Method for producing at least one device in compressive strained semiconductor Electricity 0 Active
US9379024B2 Method for manufacturing a microelectronic device including depositing identical or different metallic layers on the same wafer Electricity 0 Active
US12408405B2 Device comprising spacers including a localised airgap and associated manufacturing methods Electricity 0 Active
US10361087B2 Process for producing an intermetallic contact based on Ni on InxGa1-xAs Electricity 0 Active
US9997395B2 Fabrication method of a stack of electronic devices Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.