Semiconductor memory structure and method for manufacturing the same
US11700724B2 · kind B2 · utility
1Cited by
6References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 14, 2021 |
| Grant date | Jul 11, 2023 |
| Priority date | — |
| Expiry date | May 14, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/116
Abstract
A semiconductor structure includes a semiconductor substrate including a first active region and a chop region. The semiconductor structure also includes a source/drain region disposed in the first active region, an isolation structure disposed in the chop region, and a gate structure extending at least across the isolation structure in the chop region. The gate structure includes a gate electrode layer and a gate lining layer lining on the gate electrode layer. The gate lining layer includes a first portion having an upper surface that is lower than a bottom surface of the source/drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.