Memory arrays and methods used in forming a memory array comprising strings of memory cells

US11700729B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Yi Hu · Boise, US
• Ramey M. Abdelrahaman · Boise, US
• Narula Bilik · Boise, US
• Daniel Billingsley · Round Rock, US
• Zhenyu Bo · Boise, US
• Joan M. Kash · Meridian, US
• Matthew J. King · Boise, US
• Andrew Li · Boise, US
• David Neumeyer · Boise, US
• Wei Yeeng Ng · Boise, US
• Yung K. Pak · Sand Hollow, US
• Chandra S. Tiwari · Boise, US
• Yiping Wang · Beijing, CN
• Lance Williamson · Boise, US
• Xiaosong Zhang · Boise, US

Key dates

• Filing date: Nov 12, 2021
• Grant date: Jul 11, 2023
• Expiry date: Nov 12, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/35

Abstract

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.