Memory management device capable of managing memory address translation table using heterogeneous memories and method of managing memory address thereby
US11704018B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2020 |
| Grant date | Jul 18, 2023 |
| Priority date | — |
| Expiry date | Sep 21, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are a GPU and a method of managing a memory address thereby. TLBs are configured using an SRAM and an STT-MRAM so that a storage capacity is significantly improved compared to a case where a TLB is configured using an SRAM. Accordingly, the page hit rate of a TLB can be increased, thereby improving the throughput of a device. Furthermore, after a PTE is first written in the SRAM, a PTE having high frequency of use is selected and moved to the STT-MRAM. Accordingly, an increase in TLB update time which may occur due to the use of the STT-MRAM having a low write speed can be prevented. Furthermore, a read time and read energy consumption can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.