Heterogeneous system on a chip scheduler
US11704155B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2020 |
| Grant date | Jul 18, 2023 |
| Priority date | — |
| Expiry date | Dec 5, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/486
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous SoC and communicatively coupled to a scheduler, wherein the directed acyclic graph corresponds to a control flow graph of tasks associated with an application executed by the heterogeneous SoC. The techniques further including determining a rank for a respective task in the directed acyclic graph, wherein the rank is based on a priority of the respective task and a slack in the directed acyclic graph. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous SoC according to the rank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.