Shared decoder circuit and method
US11705175B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 8, 2022 |
| Grant date | Jul 18, 2023 |
| Priority date | — |
| Expiry date | Aug 8, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a plurality of registers, each register including SRAM cells, a read port configured to receive a read address, a write port configured to receive a write address, a selection circuit, a latch circuit, and a decoder coupled in series between the read and write ports and the plurality of registers, and a control circuit. Responsive to a clock signal and read and write enable signals, the control circuit causes the selection circuit, the latch circuit, and the decoder to select a first register of the plurality of registers in a read operation based on the read address, and select a second register of the plurality of registers in a write operation based on the write address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.