Metal-insulator-semiconductor transistors with gate-dielectric/semiconductor interfacial protection layer
US11705511B2 · kind B2 · utility
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29Claims
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Key dates
| Filing date | Aug 16, 2017 |
| Grant date | Jul 18, 2023 |
| Priority date | — |
| Expiry date | Oct 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures, devices and methods are provided for forming an interface protection layer (204) adjacent to a fully or partially recessed gate structure (202) of a group III nitride, a metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) device or a metal-insulator-semiconductor field-effect transistor (MIS-FET) device, and forming agate dielectric (114) disposed the interface protection layer (204).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.