Memory controller and operating method thereof
US11709606B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2021 |
| Grant date | Jul 25, 2023 |
| Priority date | — |
| Expiry date | Aug 30, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller controls a memory device including memory blocks, and can equalize wear levels of cores for controlling memory devices. The memory controller includes: cores for controlling the zones; a reset information controller for generating reset count values representing a number of reset requests input with respect to the zones, in response to a reset request, and generating reset count sum values obtained by summing reset count values of zones controlled by each of the cores; and a wear level manager for controlling the cores such that a core that is different from a first core having a highest reset count sum value from among the cores controls some of zones controlled by the first core according to whether a difference value between the highest reset count sum value and a lowest reset count sum value from among the reset count sum values exceeds a threshold difference value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.