Multi-stage memory device performance notification
US11709617B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2020 |
| Grant date | Jul 25, 2023 |
| Priority date | — |
| Expiry date | Sep 8, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for multi-stage memory device performance notification are described. A memory system may include a first set of memory cells of a first type associated with a first performance level and a second set of memory cells of a second type associated with a second performance level. The memory system may have an interface and a control circuit coupled with the first and second sets of memory cells. The control circuit may be configured to determine a first parameter associated with a transition between the first performance level and the second performance level. The control circuit may also be configured to store the first parameter in a first register based at least in part on determining the first parameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.