Interposer and semiconductor package including the same
US11710673B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2021 |
| Grant date | Jul 25, 2023 |
| Priority date | — |
| Expiry date | Sep 27, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/1058
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package including a first package substrate, a first semiconductor chip on the first package substrate, a first conductive connector on the first package substrate and laterally spaced apart from the first semiconductor chip, an interposer substrate on the first semiconductor chip and electrically connected to the first package substrate through the first conductive connector, the interposer substrate including a first portion overlapping the first semiconductor chip and a plurality of upper conductive pads in the first portion, a plurality of spacers on a lower surface of the first portion of the interposer substrate and positioned so as not to overlap the plurality of upper conductive pads in a plan view, and an insulating filler between the interposer substrate and the first package substrate may be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.