Patent · US Active

Semiconductor package structure

US11710688B2 · kind B2 · utility

1Cited by

0References

20Claims

0Family size

Assignee

MEDIATEK INC. · TW

Inventors

Hsing-Chih Liu · Baoshan, TW
Zheng Zeng · San Jose, US
Che-Hung Kuo · Hsinchu, TW

Key dates

Filing date	Jun 30, 2021
Grant date	Jul 25, 2023
Priority date	—
Expiry date	Jun 30, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/181
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor package structure includes a frontside redistribution layer, a stacking structure, a backside redistribution layer, a first intellectual property (IP) core, and a second IP core. The stacking structure is disposed over the frontside redistribution layer and comprises a first semiconductor die and a second semiconductor die over the first semiconductor die. The backside redistribution layer is disposed over the stacking structure. The first IP core is disposed in the stacking structure and is electrically coupled to the frontside redistribution layer through a first routing channel. The second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is separated from the first routing channel and electrically insulated from the frontside redistribution layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.