Patent · US Active

Semiconductor device fabrication method

US11710780B2 · kind B2 · utility

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24References
12Claims
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Key dates

Filing dateFeb 1, 2021
Grant dateJul 25, 2023
Priority date
Expiry dateSep 12, 2041

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D86/215
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Semiconductor device fabrication method is provided. The method includes providing a substrate; forming a first semiconductor layer on the substrate; forming a stack of semiconductor layer structures on the first semiconductor layer, each of the semiconductor layer structures comprising a second semiconductor layer and a third semiconductor layer on the second semiconductor layer, the second and third semiconductor layers having at least a common compound element, and the third semiconductor layer and the first semiconductor layer having a same semiconductor compound; performing an etching process to form a fin structure; performing a selective etching process on the second semiconductor layer to form a first air gap between the first semiconductor layer and the third semiconductor layer and a second air gap between each of adjacent third semiconductor layers in the stack of one or more semiconductor layer structures; and filling the first and second air gaps with an insulator layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.