Low gate-count encoding algorithm and hardware of flexible rate GLDPC ECC
US11711099B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2022 |
| Grant date | Jul 25, 2023 |
| Priority date | — |
| Expiry date | Mar 23, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1102
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems, devices, and methods for encoding information bits for storage, including encoding information bits and balance bits to obtain a first bit chunk of a first arrangement; permuting the first bit chunk to obtain a second bit chunk of a second arrangement; encoding the second bit chunk to obtain a third bit chunk of the second arrangement; permuting a first portion of the third bit chunk to obtain a fourth bit chunk of the first arrangement, and encoding the fourth bit chunk to obtain a fifth bit chunk of the first arrangement; permuting a second portion of the third bit chunk, and adjusting the balance bits based on the fifth bit chunk and the permutated second portion of the third bit chunk; adjusting the first arrangement based on the adjusted balance bits, and obtaining a codeword based on the adjusted first arrangement; and transmitting the codeword to a storage device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.