Three-dimensional memory devices having isolation structure for source select gate line and methods for forming the same

US11711921B2 · kind B2 · utility

Assignee

• YANGTZE MEMORY TECHNOLOGIES CO., LTD. · CN

Inventors

• Zhen Guo · Shanghai, CN
• Jingjing Geng · 红钢城街道, CN
• Bin Yuan · 红钢城街道, CN
• Jiajia Wu · Meekrap-oord, CN
• Xiangning Wang · 红钢城街道, CN
• Zhu Yang · 红钢城街道, CN
• Chen Zuo · Beijing, CN

Key dates

• Filing date: Oct 29, 2020
• Grant date: Jul 25, 2023
• Expiry date: May 18, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2223/54426
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, an isolation structure, and an alignment mark. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. The alignment mark extends vertically into the substrate and is coplanar with the isolation structure.