RISC-V-based 3D interconnected multi-core processor architecture and working method thereof

US11714649B2 · kind B2 · utility

Assignee

• SHANDONG LINGNENG ELECTRONIC TECHNOLOGY CO., LTD. · CN

Inventors

• Gang Wang · Beijing, CN
• Jinzheng Mou · Jinan, CN
• Yang-Soo An · Daejeon, KR
• Moujun Xie · Jinan, CN
• Benyang Wu · Jinan, CN
• Zesheng Zhang · Jinan, CN
• Wenyong Hou · Jinan, CN
• Yongwei Wang · Dalian, CN
• Zixuan Qiu · Jinan, CN
• Xintan Li · Jinan, CN

Key dates

• Filing date: Dec 1, 2021
• Grant date: Aug 1, 2023
• Expiry date: Dec 1, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F15/7889
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An RISC-V-based 3D interconnected multi-core processor architecture and a working method thereof. The RISC-V-based 3D interconnected multi-core processor architecture includes a main control layer, a micro core array layer and an accelerator layer, wherein the main control layer includes a plurality of main cores which are RISC-V instruction set CPU cores, the micro core array layer includes a plurality of micro unit groups including a micro core, a data storage unit, an instruction storage unit and a linking controller, wherein the micro core is an RISC-V instruction set CPU core that executes partial functions of the main core; the accelerator layer is configured to optimize a running speed of space utilization for accelerators meeting specific requirements, wherein some main cores in the main control layer perform data interaction with the accelerator layer, the other main cores interact with the micro core array layer.