Managing power loss recovery using an oldest section write policy for an address mapping table in a memory sub-system
US11714748B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2022 |
| Grant date | Aug 1, 2023 |
| Priority date | — |
| Expiry date | Mar 1, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logical-to-physical (L2P) address mapping table is maintained, wherein a plurality of sections of the L2P address mapping table is cached in a volatile memory device. A journal entry count is maintained reflecting a number of L2P journal entries associated with an L2P journal. It is determined that the journal entry count satisfies a first threshold criterion. In response to determining that the journal entry count satisfies the first threshold criterion, a writing of the L2P journal to a non-volatile memory device is triggered. A written journal count reflecting a number of L2P journals written to the non-volatile memory device is maintained. In response to determining that the written journal count satisfies a second threshold criterion, a first section of the plurality of sections of the L2P address mapping table is identified. The first section of the L2P address mapping table is written to the non-volatile memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.