NoC relaxed write order scheme
US11714779B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2020 |
| Grant date | Aug 1, 2023 |
| Priority date | — |
| Expiry date | Apr 2, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments herein describe a SoC that includes a NoC that supports both strict and relax ordering requests. That is, some applications may require strict ordering where requests transmitted from the same ingress logic to different egress logic blocks are performed sequentially. However, other applications may not require strict ordering, such as interleaved writes to memory. In those applications, relax ordering can be used were the same ingress logic block can transmit multiple requests to different egress logic blocks in parallel. For example, an ingress logic block may receive a first request that is indicated as being a relaxed ordered request. After transmitting the request to an egress logic block, the ingress logic block may receive a second request. The ingress logic block can transmit the second request to a different egress logic block without waiting for a response for the first request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.