Optimization of physical cell placement for integrated circuits
US11714944B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2020 |
| Grant date | Aug 1, 2023 |
| Priority date | — |
| Expiry date | Jul 1, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a method for optimizing an integrated circuit physical design for an integrated circuit. A physical design graph includes a plurality of physical design sub-configurations, each including a placement of a group of physical cells and having annotated characteristics. The method includes identifying, in the integrated circuit physical design, a first physical design sub-configuration including a first placement of a first group of the physical cells and having first annotated characteristics, the first annotated characteristics being outside target characteristics. The method includes selecting from the physical design graph, based on the first group of the physical cells and the target characteristics, at least a second physical design sub-configuration including a second placement of the first group of the physical cells and being within the target characteristics. The method includes replacing the first physical design sub-configuration in the integrated circuit physical design with the second physical design sub-configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.