Accelerating neural networks with low precision-based multiplication and exploiting sparsity in higher order bits
US11714998B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2020 |
| Grant date | Aug 1, 2023 |
| Priority date | — |
| Expiry date | Mar 15, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus to facilitate accelerating neural networks with low precision-based multiplication and exploiting sparsity in higher order bits is disclosed. The apparatus includes a processor comprising a re-encoder to re-encode a first input number of signed input numbers represented in a first precision format as part of a machine learning model, the first input number re-encoded into two signed input numbers of a second precision format, wherein the first precision format is a higher precision format than the second precision format. The processor further includes a multiply-add circuit to perform operations in the first precision format using the two signed input numbers of the second precision format; and a sparsity hardware circuit to reduce computing on zero values at the multiply-add circuit, wherein the processor to execute the machine learning model using the re-encoder, the multiply-add circuit, and the sparsity hardware circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.