Memory device and program operation thereof
US11715523B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2021 |
| Grant date | Aug 1, 2023 |
| Priority date | — |
| Expiry date | Jan 11, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5671
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. The peripheral circuit is configured to program a row of memory cells using a first program voltage and verify the programmed row of memory cells using a verify voltage and a sample voltage smaller than the verify voltage. The peripheral circuit is also configured to obtain a first number of memory cells of the programmed row of memory cells based on the sample voltage. The peripheral circuit is further configured to predict, based on the first number of memory cells and the sample voltage, a second number of memory cells of the programmed row of memory cells that fail to pass the verification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.