Decoupling layer to reduce underfill stress in semiconductor devices
US11715928B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2019 |
| Grant date | Aug 1, 2023 |
| Priority date | — |
| Expiry date | Nov 28, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01S5/0261
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An integrated circuit assembly includes a support (e.g., package substrate or circuit board) and a semiconductor die including a device. The semiconductor die is mounted to the support with the device facing the support. The device can be, for example, a quantum well laser device or a photonics device. A layer of decoupling material is on the device. An underfill material is between the semiconductor die and the support, where the decoupling material is between the device and the underfill material. The decoupling layer decouples stress from transferring from the underfill material into the device. For example, the decoupling material forms only weak bonds with the underfill material and/or a passivation layer on the device, in an embodiment. Weak bonds include non-covalent bonds and non-ionic bonds, for example. The decoupling material can be, for instance, a PTFE film, a poly(p-xylylene) film, a fluorocarbon, or a compound lacking free hydroxyl groups.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.