Semiconductor memory devices having stacked structures therein that support high integration

US11716844B2 · kind B2 · utility

Assignee

• SAMSUNG ELECTRONICS CO., LTD. · KR

Inventors

• Sangjae Lee · Dokdo Island, KR
• Jaehyung Kim · Seoul, KR
• Dongseog Eun · Seongnam-si, KR

Key dates

• Filing date: Aug 4, 2020
• Grant date: Aug 1, 2023
• Expiry date: Jan 18, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/40

Abstract

A semiconductor device includes an upper stack structure extending on a lower stack structure, which extends on an underlying substrate. A channel structure extends through the upper stack structure and the lower stack structure. The lower stack structure includes a first lower electrode layer disposed adjacent to an interface between the lower stack structure and the upper stack structure, and a second lower electrode layer disposed adjacent a center of the lower stack structure. The upper stack structure includes a first upper electrode layer disposed adjacent to the interface, and a second upper electrode layer disposed adjacent a center of the upper stack structure. At least one of the first lower electrode layer and the first upper electrode layer is thicker than the second lower electrode layer. At least one insulating layer is disposed between the first lower electrode layer and the first upper electrode layer.