Selective generation of miss requests for cache lines
US11720499B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 28, 2020 |
| Grant date | Aug 8, 2023 |
| Priority date | — |
| Expiry date | Dec 28, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphics pipeline includes a texture cache having cache lines that are partitioned into a plurality of subsets. The graphics pipeline also includes one or more compute units that selectively generates a miss request for a first subset of the plurality of subsets of a cache line in the texture cache in response to a cache miss for a memory access request to an address associated with the first subset of the cache line. In some embodiments, the cache lines are partitioned into a first sector and a second sector. The compute units generate miss requests for the first sector, and bypass generating miss requests for the second sector, in response to cache misses for memory access requests received during a request cycle being in the first sector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.