Control circuit of memory device
US11721374B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 29, 2022 |
| Grant date | Aug 8, 2023 |
| Priority date | — |
| Expiry date | Jun 29, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a local input/output circuit and a main input/output circuit. The local input/output circuit is configured to generate a first local write signal based on a first global write signal and a second global write signal, and configured to transmit the first local write signal to a plurality of first bit lines. The main input/output circuit include a first latch and logic elements. The first latch is configured to generate a first bit write mask signal based on a clock signal. The logic elements are configured to generate the first global write signal and the second global write signal based on the clock signal and the first bit write mask signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.