Configuration of a memory device for programming memory cells
US11721396B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2020 |
| Grant date | Aug 8, 2023 |
| Priority date | — |
| Expiry date | Nov 6, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memories having a controller configured to perform methods during programming operations including apply a first voltage level to a data line selectively connected to a selected memory cell selected, apply a lower second voltage level to a select gate connected between the data line and the memory cell, decrease the voltage level applied to the data line from the first voltage level to a third voltage level while continuing to apply the second voltage level to the select gate, increase the voltage level applied to the select gate from the second voltage level to a fourth voltage level after the voltage level of the data line settles to the third voltage level, and apply a programming voltage to the memory cell after increasing the voltage level applied to the select gate to the fourth voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.