Method for testing semiconductor dies and test structure
US11726138B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 2021 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | Dec 21, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2886
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method includes providing a test structure above a tester, wherein the test structure includes a load board including a first and second connectors, a first socket electrically connected to the first and second connectors of the load board, and a second socket electrically isolated from the first connector of the load board and electrically connected to the second connector of the load board. A first and second semiconductor dies are disposed respectively on the first and second sockets. A test signal to the first semiconductor die and the second semiconductor die through the second connector of the load board are simultaneously applied by using the tester. A first signal of the first semiconductor die through the first connector is read by using the tester. Whether the first semiconductor die is disturbed by the second semiconductor die is determined according to the first signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.