Handling memory errors identified by microprocessors
US11726873B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2021 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | Dec 20, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0238
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method and apparatus to optimize repair in a memory module based on hardware errors identified by microprocessors and a configurable error handling policy. For example, the error handling policy can have a configuration file identifying an amount of repair resources available in the memory module as manufactured. Repair status data can be stored in the memory module to determine repair resources currently available for repair. Further, the error handling policy can be configured with a list of high risk memory addresses prioritized for repair. The list can be used to schedule proactive repair in response to memory errors that would otherwise not be repaired during a typical restarting of the computer system having the memory module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.