Network interface device with bus segment width matching
US11726928B2 · kind B2 · utility
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3References
20Claims
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Key dates
| Filing date | Jun 24, 2021 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | Aug 6, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/3808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A network interface device has a data source, a data sink and an interconnect configured to receive data from the data source and to output data to the data sink. The interconnect has a memory having memory cells. Each memory cell has a width which matches a bus segment width. The memory is configured to receive a first write output with a width corresponding to the bus segment width. The write output comprises first data to be written to a first memory cell of the memory, the first data being from the data source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.