Three-dimensional NAND memory device and method of forming the same
US11728303B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2021 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | May 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is provided. The semiconductor device includes a base layer having a first side for forming memory cells and a second side that is opposite to the first side. The semiconductor device includes a stack of alternating word line layers and insulating layers that is positioned over the first side of the base layer, where the stack includes a first region and a second region. A channel structure extends through the first region of the stack in a vertical direction and further extends into the base layer from the first side. A plurality of connection structures are formed over the second side of the base layer and include a first connection structure that is coupled to the channel structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.