Trench structures for three-dimensional memory devices
US11729971B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2021 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | Dec 20, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.