3D memory devices
US11729972B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2020 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | Jan 12, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is disclosed. The semiconductor device includes a channel structure on a substrate and extending in a first direction perpendicular to a top surface of the substrate; a plurality of gate electrodes on the substrate and spaced apart from one another in the first direction on a sidewall of the channel structure; and a gate insulating layer between each of the plurality of gate electrodes and the channel structure, wherein the channel structure includes a body gate layer extending in the first direction; a charge storage structure surrounding a sidewall of the body gate layer; and a channel layer surrounding sidewall of the charge storage structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.