Multi-division staircase structure of three-dimensional memory device and method for forming the same
US11729977B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 21, 2021 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | Jan 25, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
A method for forming a staircase structure of a memory device includes the following operations. A first number of divisions are formed at different depths along a first direction in a stack structure and a trench structure between adjacent divisions, the stack structure comprising interleaved sacrificial material layers and dielectric material layers. A plurality of stairs are formed along a second direction. Each of the plurality of stairs includes the first number of divisions, and each of the divisions includes a first number of sacrificial portions. The second direction is perpendicular to the first direction. An insulating portion is formed in the trench structure. A top sacrificial portion is formed on a top surface of each of the first number of divisions and in contact with the insulating portion. The top sacrificial portion is replaced with a conductor portion through a slit structure in the insulating portion and in contact with the top sacrificial portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.