Electronic device including thermal stability enhanced layer including homogeneous material having Fe-O bond
US11730062B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Sep 25, 2020 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | Oct 20, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device may include a semiconductor memory, and the semiconductor memory may include a magnetic tunnel junction (MTJ) structure including a free layer, a pinned layer, and a tunnel barrier layer, the free layer having a variable magnetization direction, the pinned layer having a fixed magnetization direction, the tunnel barrier layer being interposed between the free layer and the pinned layer; and a thermal stability enhanced layer (TSEL) including a homogeneous material having an Fe—O bond.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.