Built in self-test of heterogeneous integrated radio frequency chiplets
US11733297B1 · kind B1 · utility
0Cited by
11References
21Claims
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Key dates
| Filing date | Mar 27, 2023 |
| Grant date | Aug 22, 2023 |
| Priority date | — |
| Expiry date | Mar 27, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318513
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An electronic assembly has a host wafer having a first circuit including wafer transistors and passive, non-transistor devices. Chiplets have a second circuit including at least one radio frequency (RF) transistor device. Electrical interconnects are between the chiplets and wafer. The electrical interconnects electrically connect the first circuit to the second circuits. Oscillators that have the wafer transistor, the RF transistor and the electrical interconnects produce a signal for built-in self-test circuits for testing an assembly design of the electronic assembly and speeds of the RF chiplet transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.