Patent · US Active

Validating memory access patterns of static program code

US11734187B2 · kind B2 · utility

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1References

25Claims

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Assignee

International Business Machines Corporation · US

Inventors

Holger Horbach · Aidlingen, DE
Cedric Lichtenau · Stuttgart, DE
Simon Weishaupt · Stuttgart, DE
Puja Sethia · Bengaluru, IN

Key dates

Filing date	Dec 14, 2021
Grant date	Aug 22, 2023
Priority date	—
Expiry date	Dec 14, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/1056
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A computer system configured to perform operations for validating memory access patterns of a static variant of a program instruction stream, the operations including randomizing a first set of input arguments, generating an address translation list for virtual addresses based on memory access patterns and storing memory accesses in a first table, and executing the static variant of the program instruction stream on the accelerator processing unit. During execution, the virtual addresses may be discarded and replaced by the addresses provided in the address translation list. The operations may include recording and storing every memory access of executing the static variant of the program instruction stream in a second table and comparing the memory access patterns stored in the second table to memory accesses patterns stored in the first table. Memory access patterns may be validated or discarded.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.