Caching of logical-to-physical mapping information in a memory sub-system
US11734189B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 16, 2021 |
| Grant date | Aug 22, 2023 |
| Priority date | — |
| Expiry date | Mar 16, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A request that specifies a logical address associated with a host-initiated operation directed at a first portion of a memory device is received. A logical to physical (L2P) table is accessed. The L2P table comprises a mapping between logical addresses and physical addresses in a second portion of the memory device. An entry in the L2P table that corresponds to the logical address is identified and is determined to point to an entry in a read cache table. Based on an entry number of the entry in the read cache table, a chunk address of a chunk from among multiple chunks of a read cache is calculated. A physical address that corresponds to the logical address specified by the request is identified by accessing the chunk of read cache. The host-initiated operation is performed at a physical location within the first portion of the memory device corresponding the physical address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.