Programmable memory cell, memory array and reading and writing method thereof
US11735279B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2020 |
| Grant date | Aug 22, 2023 |
| Priority date | — |
| Expiry date | Dec 4, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/84
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure in the field of memory technology proposes a programmable storage cell, a programmable storage array and a reading and writing method for the programmable storage array. The programmable storage cell includes: a first anti-fuse element connected between a first power terminal and an output terminal, a second anti-fuse element connected between the second power terminal and the output terminal, and a third switch unit connected to the output terminal, a third power terminal and a position signal terminal, where the third switch unit responds to the signal from the position signal terminal so as to connect the third power terminal and the output terminal. The programmable storage cell has a simple structure and a high reading speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.