Memory device and operating method of the same
US11735280B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2021 |
| Grant date | Aug 22, 2023 |
| Priority date | — |
| Expiry date | Aug 13, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is disclosed, including a bit cell storing a bit data. The bit cell includes multiple first transistors coupled to a node, multiple second transistors each coupled in series to a corresponding one of the first transistors, and at least one third transistor. The first transistors are turned on in response to a control signal. The second transistors are turned on in response to a first word line signal. The at least one third transistor has a control terminal to receive a second word line signal. In a programming mode of the memory device, the at least one third transistor provides, in response to the second word line signal, an adjust voltage to the node. The adjust voltage is associated with a voltage level of a first terminal of the at least one third transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.