Patent · US Active

Integrated circuit devices with an engineered substrate

US11735460B2 · kind B2 · utility

0Cited by

9References

20Claims

0Family size

Assignee

Qromis, Inc. · US

Inventors

Vladimir Odnoblyudov · Danville, US
Dilip Risbud · San Jose, US
Ozgur Aktas · Santa Clara, US
Cem Basceri · Boise, US

Key dates

Filing date	Jul 28, 2021
Grant date	Aug 22, 2023
Priority date	—
Expiry date	Feb 11, 2042

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/111
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit device includes an engineered substrate including a substantially single crystal layer and a buffer layer coupled to the substantially single crystal layer. The integrated circuit device also includes a plurality of semiconductor devices coupled to the buffer layer. The plurality of semiconductor devices can include a first power device coupled to a first portion of the buffer layer and a second power device coupled to a second portion of the buffer layer. The first power device includes a first channel region comprising a first end, a second end, and a first central portion disposed between the first end and the second end. The second power device includes a second channel region comprising a third end, a fourth end, and a second central portion disposed between the third end and the fourth end.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.