System and method for removing scalloping and tapering effects in high aspect ratio through-silicon vias of wafers
US11735478B2 · kind B2 · utility
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9Claims
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Key dates
| Filing date | Apr 29, 2021 |
| Grant date | Aug 22, 2023 |
| Priority date | — |
| Expiry date | Dec 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3083
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing vias in a silicon wafer, the silicon wafer having a <110> crystal orientation, and having a <111> plane that is perpendicular to a surface of the wafer, tilted by 35.26°, the method comprising the steps of providing a mask having a rhomboidal-shaped opening onto a surface of the silicon wafer, such that edges of the rhomboidal-shaped opening line up with a <111> plane of a crystalline structure of the silicon wafer, etching a hole in the silicon wafer at the rhomboidal-shaped opening, and polishing the hole after the etching by a anisotropic etching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.