Integrated circuit structures with source or drain dopant diffusion blocking layers
US11735630B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2019 |
| Grant date | Aug 22, 2023 |
| Priority date | — |
| Expiry date | Nov 29, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the disclosure include integrated circuit structures having source or drain dopant diffusion blocking layers. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over a channel region of the fin, the gate structure having a first side opposite a second side. A first source or drain structure is at the first side of the gate structure. A second source or drain structure is at the second side of the gate structure. The first and second source or drain structures include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is in contact with the channel region of the fin, and the second semiconductor layer is on the first semiconductor layer. The first semiconductor layer has a greater concentration of germanium than the second semiconductor layer, and the second semiconductor layer includes boron dopant impurity atoms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.