Non-selective epitaxial source/drain deposition to reduce dopant diffusion for germanium NMOS transistors

US11735670B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Glenn A. Glass · Portland, US
• Anand S. Murthy · Beaverton, US
• Karthik Jambunathan · Hillsboro, US
• Cory Bomberger · Portland, US
• Tahir Ghani · Portland, US
• Jack T. Kavalieros · Portland, US
• Benjamin Chu-Kung · Portland, US
• Seung Hoon Sung · Beaverton, US
• Siddharth Chouksey · Portland, US

Key dates

• Filing date: Oct 8, 2021
• Grant date: Aug 22, 2023
• Expiry date: Feb 10, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0167
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.