Clock signal delay path unit and semiconductor memory device including the same
US11736097B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2022 |
| Grant date | Aug 22, 2023 |
| Priority date | — |
| Expiry date | Mar 15, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.