Memory package, semiconductor device, and storage device
US11736098B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2022 |
| Grant date | Aug 22, 2023 |
| Priority date | — |
| Expiry date | Jul 17, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00247
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory package includes a plurality of memory chips, and an interface chip relaying communications between a controller and the plurality of memory chips and receiving a plurality of signals from the plurality of memory chips. The interface chip includes receivers outputting a data signal and a raw clock signal based on the plurality of signals, a delay circuit outputting a delay clock signal by applying an offset delay corresponding to ½ of one unit interval of the data signal and an additional delay to the raw clock signal, and a sampler sampling the data signal in synchronization with a clock signal. The delay circuit outputs the clock signal generated by removing the offset delay from the delay clock signal when the delay clock signal and the data signal have a phase difference corresponding to one unit interval of the data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.